The present invention relates to the field of managing the reception of data received by a device. More particularly, the present invention relates to the field of managing the reception of data received on a channel by a device.
The IEEE standard, xe2x80x9cIEEE 1394 Standard For A High Performance Serial Bus,xe2x80x9d Draft ratified in 1995, is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. Isochronous data transfers are real-time transfers which take place such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. The IEEE 1394-1995 standard bus architecture provides up to sixty-four (64) channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional data transfer operations which take place as soon as possible and transfer an amount of data from a source to a destination.
The IEEE 1394-1995 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394-1995 standard defines a digital interface for the applications thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394-1995 standard is very thin in size compared to other bulkier cables used to connect such devices. Devices can be added and removed from an IEEE 1394-1995 bus while the bus is active. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique identification number on the bus structure. Each node provides an identification ROM, a standardized set of control registers and its own address space.
The IEEE 1394-1995 standard defines a protocol as illustrated in FIG. 1. This protocol includes a serial bus management block 10 coupled to a transaction layer 12, a link layer 14 and a physical layer 16. The physical layer 16 provides the electrical and mechanical connection between a device or application and the IEEE 1394-1995 cable. The physical layer 16 also provides arbitration to ensure that all devices coupled to the IEEE 1394-1995 bus have access to the bus as well as actual data transmission and reception. The link layer 14 provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgement protocol, and isochronous data transport, providing real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer 12 supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The serial bus management block 10 contains an isochronous resource manager for managing isochronous data transfers. The serial bus management block 10 also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
As discussed above, an IEEE 1394-1995 device includes the capability to transmit and receive isochronous data over multiple channels. The IEEE 1394-1995 standard provides for up to sixty-four different isochronous channels to be used within an IEEE 1394-1995 network of devices. However, in current implementations, certain IEEE 1394-1995 devices are being built with the capability to only transmit and receive isochronous data over a subset of less than sixty-four channels. When receiving data on an isochronous channel, that data must be processed by the receiving device. This processing includes any or all of displaying, manipulating, forwarding and storing. Often, data received on different isochronous channels is processed differently, depending on the type of device from which the data is received, the type of data that is received and the desired use of the data. If data received on an isochronous channel is not received and processed efficiently, errors in the display or use of the data can result.
An apparatus for dispatching a processing element to a program location based on a channel number of received data includes a channel pointer register having a number of storage locations each with a channel number field, a valid bit field and a corresponding instruction pointer field. When an isochronous channel is allocated for use for reception, the host device programs the channel number and a corresponding instruction pointer value into a storage location. When a storage location is programmed, a valid bit within that storage location is also preferably set. The corresponding instruction pointer value points to a series of instructions which are to be used to process data received on that isochronous channel. When isochronous data is then received, the channel number on which the data is received is compared to the channel numbers within the valid storage locations in the channel pointer register. If one of the channel numbers within a valid storage location matches the channel number of the received data, then the corresponding instruction pointer value is output and the data is processed according to a series of instructions beginning at the location specified by the corresponding instruction pointer value. Otherwise, if the channel number of the received data does not match any of the channel numbers within valid storage locations then a default instruction pointer value is output and the received data is processed according to a series of instructions beginning at the location specified by the default instruction pointer value. The series of instructions beginning at the location specified by the default instruction pointer value are used to broadcast data received on a single channel on all appropriate channels, multicast data received on a single channel to a select group of channels, handle errors and exceptions related to received data and unprogrammed channel numbers, ignore data received on a channel, route data received on a first channel to one or more different channels, to monitor the active channels on the bus and any other appropriate action to process data received on a channel with no corresponding valid instruction pointer value.
In one aspect of the invention, a method of processing received data having a real-time component comprises receiving data having the real-time component on a received channel number, comparing the received channel number to stored channel numbers within a plurality of memory locations, each of the plurality of memory locations including a corresponding address value specifying a starting address for a series of instructions for processing data received on a corresponding stored channel number, providing the corresponding address value corresponding to the stored channel number matching the received channel number as an output address value if one of the stored channel numbers matches the received channel number and providing a default address value as the output address value if none of the stored channel numbers matches the received channel number. The method further includes allocating an allocated channel number for receiving data and programming the allocated channel number and a corresponding allocated address value into one of the memory locations to form the stored channel number and the corresponding address value for the memory location. The default address value specifies a default starting address for a series of default instructions for processing data received on the received channel number. The series of default instructions controls broadcast of data received on the received channel number out on one or more different channel numbers. The series of default instructions controls multicast of data received on the received channel number out on a group of channel numbers. The series of default instructions handles errors and exceptions related to data received on the received channel number. The series of default instructions ignores data received on the received channel number. The series of default instructions reroutes data received on the received channel number on one or more different channel numbers. The series of default instructions monitors active channels on which data is received. The memory locations are locations within a register. The method further includes programming a valid bit within a programmed memory location. The data is preferably isochronous data. Comparing is performed by a comparator which is provided the stored channel numbers in parallel.
In another aspect of the invention, an apparatus for processing received data having a real-time component comprises a plurality of storage locations each including a channel number field to store a stored channel number and an instruction pointer field to store a stored address value, a comparing circuit coupled to the plurality of storage locations and configured to receive a received channel number on which data having a real-time component is received, wherein the comparing circuit compares the stored channel numbers to the received channel number to determine if any of the stored channel numbers match the received channel number and an output circuit coupled to the comparing circuit and to the plurality of storage locations to provide the stored address value within the storage location having the stored channel number matching the received channel number as an output address value. The comparing circuit compares the stored channel numbers to the received channel number in parallel. The apparatus further comprises a default storage location coupled to the output circuit to store a default address value and provide the default address value as the output address value if none of the stored channel numbers match the received channel number. The default address value specifies a default starting address for a series of default instructions for processing data received on the received channel number. The series of default instructions controls broadcast of data received on the received channel number out on one or more different channel numbers. The series of default instructions controls multicast of data received on the received channel number out on a group of channel numbers. The series of default instructions handles errors and exceptions related to data received on the received channel number. The series of default instructions ignores data received on the received channel number. The series of default instructions reroutes data received on the received channel number on one or more different channel numbers. The series of default instructions monitors active channels on which data is received. The storage locations further each include a valid bit. The storage locations are programmable. The apparatus further comprises a host device coupled to the plurality of storage locations to program the stored channel numbers and the stored address values. The host device sets the valid bit within the storage location when the storage location is programmed. The apparatus further comprises a processing device coupled to the output circuit to receive the output address value, wherein the output address value specifies a beginning location for a series of instructions to be used to process the data received on the received channel number. The data is preferably isochronous data.
In another aspect of the invention, a receiving device configured to receive data from one or more remote devices comprises an interface circuit configured to receive data on one or more received channel numbers, a plurality of storage locations each including a channel number field to store a stored channel number, an instruction pointer field to store a stored address value and a valid bit having a first state and a second state, wherein when the valid bit for a storage location is in the first state the storage location is valid, a comparing circuit coupled to the interface circuit and to the plurality of storage locations to receive the received channel number corresponding to received data and compare the stored channel numbers to the received channel number to determine if any of the stored channel numbers match the received channel number, a default storage location for storing a default address value and an output circuit coupled to the comparing circuit, to the plurality of storage locations and to the default storage location to provide the stored address value within the storage location having the stored channel number matching the received channel number as an output address value, if one of the stored channel numbers within valid storage locations matches the received channel number, and to provide the default address value as the output address value if none of the stored channel numbers within the valid storage locations match the received channel number, wherein the default address value specifies a default starting address for a series of default instructions for processing data received on the received channel number. The comparing circuit compares the stored channel numbers to the received channel number in parallel. The comparing circuit only compares stored channel numbers within the valid storage locations to the received channel number. The storage locations are programmable. The host device sets the valid bit within the storage location when the storage location is programmed. The receiving device further comprises a processing device coupled to the output circuit to receive the output address value, wherein the output address value specifies a beginning location for a series of instructions to be used to process the data received on the received channel number. The series of default instructions controls broadcast of data received on the received channel number out on one or more different channel numbers. The series of default instructions controls multicast of data received on the received channel number out on a group of channel numbers. The series of default instructions handles errors and exceptions related to data received on the received channel number. The series of default instructions ignores data received on the received channel number. The series of default instructions reroutes data received on the received channel number on one or more different channel numbers. The series of default instructions monitors active channels on which data is received.